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Instruction timings
Instruction timings
The main clock in the CPC is 16Mhz This is provided to the Gate-Array which generates the other clocks.
The Gate Array has the following roles:
- generation of a 1Mhz clock for the CRTC and AY-3-8912
- generation of a 4Mhz clock for the CPU
- arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array)
Every microsecond:
- The CRTC generates a memory address using it's MA and RA signal outputs
- The Gate-Array fetches two bytes for each address
The video hardware is given priority so that the display is not disrupted
The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing while the video-hardware is accessing it. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.
The following table gives the complete execution time for all CPU instructions
These timings have been measured
| Mneumonic(s) | Number of microseconds |
|---|---|
| NOP | 1 |
| LD rp,nnnn | 3 |
| INC rp DEC rp |
2 |
| INC r DEC r |
1 |
| LD r,n | 2 |
| RLCA RRCA RLA RRA |
1 |
| EX AF,AF' | 1 |
| ADD HL,rp | 3 |
| LD A,(BC) LD (BC),A LD (DE),A LD A,(DE) |
2 |
| DJNZ dd | b-1=0 : 3, b-1<>0 : 4 |
| JR dd | 3 |
| JR cc,dd | nc : 2, c : 3 |
| LD (nnnn),HL LD HL,(nnnn) |
5 |
| DAA | 1 |
| LD A,(nnnn) LD (nnnn),A |
4 |
| INC (HL) DEC (HL) |
3 |
| LD (HL),nn | 3 |
| SCF CCF CPL |
1 |
| LD r,r | 1 |
| LD r,(HL) LD (HL),r |
2 |
| HALT | 1variable |
| ADD A,r ADC A,r SUB r SBC A,r |
1 |
| ADD A,(HL) ADC A,(HL) SUB A,(HL) SBC A,(HL) |
2 |
| AND r XOR r OR r CP r |
1 |
| AND (HL) XOR (HL) OR (HL) CP (HL) |
2 |
| RET | 3 |
| RET cc | nc : 2, c : 4 |
| POP rp | 3 |
| PUSH rp | 4 |
| JP cc,nnnn | nc : 3, c : 3 |
| JP nnnn | 3 |
| CALL nnnn | 5 |
| CALL cc,nnnn | nc : 3, c : 5 |
| ADD A,n ADC a,n SUB n SBC A,n |
2 |
| AND n XOR n OR n CP n |
2 |
| RST 0 RST 1 RST 2 RST 3 RST 4 RST 5 RST 6 RST 7 |
4 |
| RLC r RRC r RR r RL r SLA r SLL r SRL r |
2 |
| RLC (HL) RRC (HL) RR (HL) RL (HL) SLA (HL) SLL (HL) SRL (HL) |
4 |
| BIT b,r RES b,r SET b,r |
2 |
| BIT b,(HL) | 3 |
| RES b,(HL) SET b,(HL) |
4 |
| IN A,(nn) OUT (nn),A |
3 |
| EXX | 1 |
| ADD IX,rp | 4 |
| LD IX,nnnn | 4 |
| LD (nnnn),IX LD IX,(nnnn) |
6 |
| INC IX DEC IX |
3 |
| INC HIX DEX HIX INC LIX DEC LIX |
2 |
| LD HIX,nn LD LIX,nn |
3 |
| INC (IX+dd) DEC (IX+dd) |
6 |
| LD (IX+dd),nn | 6 |
| LD r,HIX LD r,LIX LD HIX,r LD LIX,r |
2 |
| LD r,(IX+dd) LD (IX+dd),r |
5 |
| ADD A,HIX ADC A,HIX SUB HIX SBC A,HIX |
2 |
| ADD A,(IX+dd) ADC A,(IX+dd) SUB (IX+dd) SBC A,(IX+dd) |
5 |
| AND (IX+dd) XOR (IX+dd) OR (IX+dd) CP (IX+dd) |
5 |
| AND HIX/XOR HIX/OR HIX/CP HIX | 2 |
| RLC (IX+dd) RRC (IX+dd) RL (IX+dd) RR (IX+dd) SLA (IX+dd) SRA (IX+dd) SLL (IX+dd) SRL (IX+dd) |
7 |
| BIT r,(IX+dd) | 6 |
| RES r,(IX+dd) SET r,(IX+dd) |
7 |
| PUSH IX PUSH IY |
5 |
| POP IX POP IY |
5 |
| EX (SP),IX | 7 |
| JP (IX) | 2 |
| EX (SP),HL | 6 |
| LD SP,IX | 3 |
| JP (HL) | 1 |
| EX DE,HL | 1 |
| IN r,(C) OUT (C),r IN F,(C) OUT (C),0 |
4 |
| SBC HL,rp ADC HL,rp |
4 |
| LD (nnnn),rp LD rp,(nnnn) (includes LD (nnnn),HL and LD (nnnn),HL with ED prefix) |
6 |
| NEG | 2 |
| IM 0 IM 1 IM 2 |
2 |
| LD I,A LD A,I LD R,A LD A,R |
3 |
| DI EI |
1 |
| LD SP,HL | 2 |
| RLD RRD |
5 |
| LDI LDD |
5 |
| OUTI OUTD |
5 |
| LDIR LDDR |
BC-1=0 : 5, BC-1<>0 : 6 |
| RETN RETI |
4 |
| DD FD prefix (note 1) |
1 |
| ED "nop" (ED 00 - ED 3F) | 2 |
| CPI | 5 |
| INI | 5 |
| CPD | 5 |
| IND | 5 |
| CPIR | BC-1=0 : 5, BC-1<>0 : 6 |
| INIR | BC-1=0 : 5, BC-1<>0 : 6 |
| OTIR | BC-1=0 : 5, BC-1<>0 : 6 |
| CPDR | BC-1=0 : 5, BC-1<>0 : 6 |
| INDR | BC-1=0 : 5, BC-1<>0 : 6 |
| OTDR | BC-1=0 : 5, BC-1<>0 : 6 |
NOTES:
- This timing applies when there are multiple DD or FD prefix's together.
- The timings for IY index register pair are identical to the timings for IX register pair.
Key:
| cc | condition code (z,nz,c,nc,p,m,po,pe) |
| r | 8-bit register (B,C,D,E,H,L,A) |
| b | Bit number (0,1,2,3,4,5,6,7) |
| n | 8 bit value |
| nnnn | 16 bit value |
| dd | 8 bit displacement |
| rp | 16-bit register (HL,DE,BC) |
| nc | condition not satisfied |
| c | condition satisfied |
Other timings
Time between acknowledge of a interrupt and execution of a interrupt
- Mode 0: (depends on instruction
- Mode 1: 5
- Mode 2: 19
1 monitor scanline: 64 microseconds
1 50Hz monitor frame: 19968 microseconds.
| Article créé le : | Vendredi 20 Novembre 2009 à 21 h 44 |
| Dernière mise à jour le : | Samedi 15 Février 2020 à 21 h 15 |
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