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Timing information for writing to CRTC on CPC+

Timing information for writing to CRTC on CPC+

Here is some information I got from Richard about timing: "After some experimentation, I have come to the conclusion that the following two factors account for the delay in writing CRTC registers on the CPC Plus/ASIC.

1. The horizontal SYNC pulse generated by the ASIC occurs 1 character later (actually 17 pixels) than that of the CRTC Type 0. The output pulse to the monitor on a CRTC Type 0 is most likely delayed by the Gate Array (not necessarily in line with the black section displayed) otherwise the horizontal position of a CPC Plus screen would be shifted to the left.

   This causes the Raster 52 interrupt to occur 1us later, causing all OUT instructions to occur 1us later than normal if the code is timed using the standard Raster 52 interrupts.

2. Writing to an ASIC CRTC register is further delayed in the ASIC by an amount of time (1us is appropriate for emulation) as compared to CRTC Type 0. This causes writes to the CRTC to have an effect 2us later than normal when combined with 1 above.

Writes to the VGA (i.e. colour changes and mode changes) are not delayed extra by the ASIC, but (like the standard CPC) the palette changes from register writes occur about 0.5us after the end of the OUT instruction. The IN instruction updates the register.

Changes in display mode on both systems (through the GA/ASIC #7Fxx) are checked internally at the end of the monitor HSYNC output. The monitor HSYNC output is delayed from the CRTC by 2us. Reg 3 values of 0,1 or 2 will all produce no monitor HSYNC (value 0 may produce 4us on some CRTC's). The Gate Array ends the HSYNC output 6 characters after the start of the CRTC HSYNC, or at the end of the CRTC HSYNC (whichever occurs first).

The monitor centres its own internal free running HSYNC to the output HSYNC pulse, hence 1 char changes to register 3 will cause shifting by 0.5 chars (1 mode 2 character).

The internal circuitry in the monitor is a combination of a Phase Locked Loop (PLL) with some analogue circuitry. This can provide fast responses to phase shifts in the output SYNC waveform, but changes in frequency of the waveform take quite some time to adjust. This can be demonstrated by changing register 2 (phase shift) which causes a fast adjustment (i.e. Approximately 8 scan lines per character, proportional to the distance between the free-running pulse and the output HSYNC pulse), or by changing register 0 which may take a number of frames to adjust (try setting register 0 to 62 or 64, and you can see the whole screen move for a few frames).

Richard"